MIG v3.1, v3.2, v3.3, v3.4 Virtex-6 FPGA QDRII+ - Changes required to Samsung simulation model for proper operation and completion of calibration

AR#	33289	Search For Another Answer
Topic	MIG
Last Updated	06/09/2011
Status	Active

Description

When I run a Virtex-6 FPGA MIG v3.1 QDRII+ simulation with a Samsung model (K7SXXXXT4C_R04.v), calibration does not complete (cal_done does not assert).

Solution

Changes to the Samsung model (K7SXXXXT4C_R04.v) are required for proper simulation operation with the Virtex-6 FPGA QDRII+ design. Edit the following within the model: 

Line 244 -  

Change from: eclk = ~K_N; 

Change to: eclk = ~K; 


Line 245 - 

Change from: eclk_b = ~K; 

Change to: eclk_b = ~K_N; 


This ensures data is presented on the correct clock. After making these changes, calibration completes successfully.