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AR# 33289

MIG v3.1, v3.2, v3.3, v3.4 Virtex-6 FPGA QDRII+ - Changes required to Samsung simulation model for proper operation and completion of calibration

Description

When I run a Virtex-6 FPGA MIG v3.1 QDRII+ simulation with a Samsung model (K7SXXXXT4C_R04.v), calibration does not complete (cal_done does not assert).

Solution

Changes to the Samsung model (K7SXXXXT4C_R04.v) are required for proper simulation operation with the Virtex-6 FPGA QDRII+ design. Edit the following within the model:

Line 244 -

Change from: eclk = ~K_N;

Change to: eclk = ~K;


Line 245 -

Change from: eclk_b = ~K;

Change to: eclk_b = ~K_N;


This ensures data is presented on the correct clock. After making these changes, calibration completes successfully.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 33289
Date Created 08/17/2009
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG