These errors are generated because these devices are missing the right column on IOs, which implies that the BUFRs in these columns are not present as well. Since the GTPs are located on the right side, the BUFRs instantiated in the design cause an unroutable situation.
To work around and resolve this issue, replace the instantiation of this BUFR with a BUFG.
1. Copy the xps_ll_temac_v2_02_a core from the install folder, $XILINX_EDK\hw]XilinxProcessorIPLib\pcores to the project local pcores folder, <Project>\pcores\.
2. Open the file, <Project>\pcores\xps_ll_temac_v2_02_a\hdl\vhdl\v5_single_sgmii_gtp_dual_1000X.vhd in a text editor. Note, for the FXT implementation, v5_single_sgmii_gtx_dual_1000X.vhd should be edited.
3. Replace lines 306-309,
-- Route RXRECLK0 through a regional clock buffer
rxrecclk0bufr : BUFR port map (I => RXRECCLK_0, O => RXRECCLK_0_BUFR,
CE => '1', CLR => '0');
with
-- Route RXRECLK0 through a global clock buffer
rxrecclk0bufr : BUFG port map (I => RXRECCLK_0, O => RXRECCLK_0_BUFR,
CE => '1', CLR => '0');
4. Save the file. Clean the generated files and reimplement the design.
NOTE:
1. The modfications should be made in the local pcores folder.
2. The above solution has not gone through official testing and will also increase the usage of BUFGs in the system.