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AR# 33297

FIFO Generator v5.3 - Release Notes and Known Issues for ISE 11.3


Keywords: CORE Generator, IP, update, fifogen, asynchronous, synchronous, common, clocks, memory, block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft

This Release Notes and Known Issues Answer Record is for the FIFO Generator v5.3 Core, released in ISE 11.3 and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues
- Device Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:


General Information

(Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be
(Xilinx Answer 22722) FIFO Generator Core now includes a User Guide in addition to a Data Sheet. Where can I find the User Guide for the FIFO Generator?
(Xilinx Answer 24712) How do I test user logic that triggers ECC SBITERR and DBITERR outputs in FIFO Generator?
(Xilinx Answer 30029) Setup/Hold time violations occur in the Unconstrained Path Report
(Xilinx Answer 31144) Differences between FIFO v4.x (and newer) cores and v3.x (and prior) cores

New Features in v5.3

- ISE 11.3 support

- Virtex-6 -L Lower-power and Virtex-6 HXT device support

- Spartan-3A\-3A DSP Automotive device support

Bug Fixes in v5.3

- Virtex-5 - Use Dout Reset feature is not supported according to the User Guide, but it is available in the GUI
- Version fixed: 5.3
- CR 502500
- AR 32737

- Last word not read out of FIFO using Virtex-6 device Built In FIFO
- Version fixed: 5.3
- CR 525041
- AR 32739

- Virtex-6 device Built-In FIFOs targeting FIFO36E1 primitives fail to generate
- Version fixed: 5.3
- CR 522794
- AR 32988

- The MSBs of DOUT are stuck at a fixed value.
- Version fixed: 5.3
- CR 525159
- AR 33213

Known Issues in v5.3

(Xilinx Answer 24003) NC-Sim warning occurs when targeting Virtex-5 devices
(Xilinx Answer 23691) Behavioral simulation models are not supported for built-in FIFO configuration
(Xilinx Answer 20291) During simulation X_FF RECOVERY and SETUP warnings occur
(Xilinx Answer 20271) Simulation error occurs on RESET
(Xilinx Answer 30226) When writing to an EMPTY FIFO, PROG_FULL might assert earlier than expected
(Xilinx Answer 31379) When importing an XCO file, user cannot change read/write clock frequencies with Built-in FIFO
(Xilinx Answer 32740) Write Data Count is not cycle accurate in behavioral model for non symmetric aspect ratios of 1:4 and 1:8 when FWFT is used
(Xilinx Answer 33395) DOUT reset value does not function correctly on Virtex-6 device Built In FIFO

Revision History
09/16/2009 - Initial Release
AR# 33297
Date Created 09/08/2009
Last Updated 09/08/2009
Status Active
Type General Article