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AR# 33298

Block Memory Generator v3.3 - Release Notes and Known Issues for ISE 11.3


Keywords: CORE Generator, mem, memory, asynch, asymmetric, nonsymmetric, non-symmetric, block RAM, RAMB, block RAM, BRAM, RAMB16, RAMB, simulation, UniSim, SimPrim, unisims, simprims, NetGen, SDF

This Release Notes and Known Issues Answer Record is for the Block Memory Generator v3.3 Core, released in ISE 11.3, and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:


General Information
The Xilinx Block Memory Generator v3.3 LogiCORE should be used in all new Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3 /-3E /-3E XA /-3A /-3 XA designs wherever block memory is required. This core supersedes the Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores, but is not a direct drop-in replacement. A Block Memory Migration Kit is available on Xilinx.com to convert Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores to the newer Block Memory Generator Core format.

Please see the Block Memory Core Migration Kit available at:

Also, see (Xilinx Answer 24848) for known issues of the migration kit, and (Xilinx Answer 29168) for changes made from pre-v2.4 XCO parameters.

A new CORE Generator feature is available to upgrade the Block Memory Generator from v2.4 to the latest core. This feature is part of CORE Generator, and it is visible only if you open an existing CORE Generator project with a previously generated Block Memory Generator v2.4 core. See the "Upgrading a Core" section of the CORE Generator User Guide (Software Manuals).

(Xilinx Answer 24712) How to test user logic that triggers ECC SBITERR and DBITERR outputs in the Block Memory Generator
(Xilinx Answer 31378) BitGen DRC Warnings Are Produced When DOA is Unused and DIA is Tied to Ground
(Xilinx Answer 31377) "ERROR:ip - build_algo_return: For the configured RAM size, the number of block RAMs used exceeds the maximum number of block RAMs in all available architectures (550)"

New Features in v3.3

- ISE 11.3 support
- Virtex-6 Lower Power and Virtex-6 HXT device support
- Spartan-3A/-3A DSP Automotive device support
- Power estimation reporting in CORE Generator GUI

Resolved Issues in v3.3

- Byte write enables incorrectly disabled in CORE Generator IP customization GUI when Spartan-3A device is selected
- Version fixed: 3.3
- CR 525957
- In version 3.2 the Byte Write Enable was disabled for Spartan-3A devices.
This has been re-enabled so that the user can now choose to set or unset Byte Write Enable.

- Async reset support not enabled in CORE Generator IP customization GUI when Spartan-6 device is selected
- Version fixed: 3.3
- CR 521107
- AR 32815
- Async reset support has been enabled in CORE Generator IP customization GUI for Spartan-6 devices. However, the Xilinx
synthesis tool generates a warning "Xst:2940 - This design infers one or more latches or registers with both an active asynchronous set and reset."

- Special reset behavior not seen on core output in Virtex-6 devices
- Version fixed : 3.3
- CR 520553
- There is a limitation in supporting special reset behavior with the priority
set to SR based on limitations in the associated Virtex-6 FPGA primitive, hence the IP has been updated
to support special reset behavior when the reset priority is set to CE only.

- In Block Memory Generator data sheet, the resource utilization for Spartan-3 FPGA is incorrect
- Version fixed : 3.3
- CR 527310
- AR 33192

Known Issues in v3.3

- Power estimation figures in the data sheet are preliminary.

(Xilinx Answer 31377) CORE Generator GUI Console displays error "For the configured RAM size, the number of block RAMs used exceeds the maximum number of 18KB block RAMs in the chosen architecture"

(Xilinx Answer 24034) Core does not generate for large memories
-The maximum size of the memory that can be generated varies depending on the machine the CORE Generator is run on. For example, a Dual Pentium-4 server running at 3.6 GHz with two Gig RAM can generate a memory core that is 1.8 MBits or 230 KBytes.
- CR 415768

(Xilinx Answer 23744) Out-of-range address input can cause the core to generate Xs on the DOUT bus

(Xilinx Answer 33322) Why do I see setup violations when I simulate my Virtex-6 FPGA SDP memory?

Device Issues
The Virtex-4 and Virtex-5 FPGA Errata are located at:
The Block Memory Generator Core is subject to all block RAM issues listed in the Errata.

Revision History
09/16/2009 - Initial Release
AR# 33298
Date Created 08/18/2009
Last Updated 09/08/2009
Status Active
Type General Article