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AR# 33309 Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 and v1.3 rev1 - Release Notes and Known Issues for ISE 11.3 and 11.5

Description

This Answer Record contains the Release Notes for the Virtex-6 FPGA LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.3, which was released in ISE DesignSuite 11.3, and the v1.3 rev1wrapper, which wasreleased in ISE 11.5.ThisAnswer Recordincludes the following:

  • General Information
  • New Features
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:

http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

  • Supports automatic generation of HDL wrapper files for the Virtex-6 FPGA Tri-Mode Ethernet MAC
  • Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII and 1000Base-X PCS/PMA configurations are supported)
  • Provides a FIFO-based example design
  • Provides a demonstration testbench for the selected configuration

(Xilinx Answer 33593) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Frequently Asked Questions (FAQ)

New Features

  • ISE 11.3 software support
  • Support for Virtex-6 HXT and Virtex-6 Lower Power devices
  • Hardware validated, including successful conformance testing at UNH IOL
  • Addition of logic in some 10/100 Mbps cases, assuring proper FCS behavior

Resolved Issues in v1.3 and later

(Xilinx Answer 33043) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.2 - "Error Place:1153 - A clock IOB / BUFGCTRL pair not placed at optimal site"

Resolved Issues in v1.3 rev1

(Xilinx Answer 34015) Virtex-6 FPGA Embedded Tri-Mode Rthernet MAC Wrapper 1.3 - The example design MMCM parameter values can cause Map errors or result in marginal operation

(Xilinx Answer 34162) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - Block RAM parameterization may result in memory collisions during simulation and erroneous operation

(Xilinx Answer 33363) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - With 16-bit client interface, the wrong clock is used to analyze some client-side Ethernet MAC signals

Known Issues in v1.3 rev1

(Xilinx Answer 33195) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - Adjusting IDELAYs to meet GMII and RGMII setup and hold requirements

(Xilinx Answer 33362) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - "Warning:Par:468 - Your design did not meet timing" seen in some configurations

(Xilinx Answer 33386) 11.3 CORE Generator software - Licenses for certain free cores are now part of the software installv

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
34162 Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - Block RAM parameterization might result in memory collisions during simulation and erroneous operation N/A N/A
34015 Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - The example design MMCM parameter values can cause Map errors or result in marginal operation N/A N/A
33195 Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Adjusting IDELAYs to meet GMII and RGMII setup and hold requirements N/A N/A

Actions

AR# 33309
Date Created 09/08/2009
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
IP
  • Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper
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