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AR# 33311 LogiCORE IP RXAUI v1.1 and v1.1 rev1 - Release Notes and Known Issues for ISE 11.3 and ISE 11.5

Description

This Answer Record contains the Release Notes for the LogiCORE IP RXAUI v1.1 Core, which was released in the 11.3 ISEsoftware, and v1.1 rev1, which was released in theISE 11.5 software. This Answer Recordincludes the following:

  • New Features
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features

  • First Release of Core.

Resolved Issues in v1.1

  • First Release of Core.

Resolved Issues in v1.1 rev1

  • (Xilinx Answer 33486) - LogiCORE XAUI v9.1 and RXAUI v1.1 - Update needed for reset logic in block level for Spartan-6 Device GTP and Virtex-6 Device GTX wrappers
  • (Xilinx Answer 33488) - LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX powerdown reset logic should be updated
  • (Xilinx Answer 33649) - LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX default setting for TXDIFFCTRL could result in electrical idle condition
  • (Xilinx Answer 34160) - LogiCORE IP RXAUI v1.1 - The Virtex-6 FPGAExample Design MMCM can causeDRC errors

Known Issues in v1.1 rev1

  • (Xilinx Answer 33489) - LogiCORE XAUI v9.1 and RXAUI v1.1 - Timing Simulation Timeouts seen in Virtex-6 FPGA Example Design
  • (Xilinx Answer 33893) - LogiCORE RXAUI v1.1 - Implementing Virtex-6 FPGA Example Designs results in MAP errors for some device packages

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
34160 LogiCORE IP RXAUI v1.1 - The Virtex-6 FPGA Example Design MMCM can cause DRC errors N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34160 LogiCORE IP RXAUI v1.1 - The Virtex-6 FPGA Example Design MMCM can cause DRC errors N/A N/A
33893 LogiCORE IP RXAUI v1.1 - Implementing Virtex-6 FPGA Example Designs results in MAP errors for some device packages N/A N/A
33649 LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX default setting for TXDIFFCTRL could result in electrical idle condition N/A N/A
33489 LogiCORE XAUI v9.1 and RXAUI v1.1 - Timing Simulation Timeouts seen in Virtex-6 FPGA 64-bit Internal Interface Example Design N/A N/A
33488 LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX powerdown reset logic should be updated N/A N/A
33486 LogiCORE XAUI v9.1 and RXAUI v1.1 - Update needed for reset logic in block level for Spartan-6 Device GTP and Virtex-6 Device GTX wrappers N/A N/A

Actions

AR# 33311
Date Created 09/10/2009
Last Updated 05/22/2012
Status Active
Type Release Notes
Devices
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
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