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AR# 33314

SPI-3 Link Layer v6.1 - Release Notes and Known Issues for ISE 11.3 software


This Release Note and Known Issues Answer Record is for the SPI-3 (POS-PHY L3) Link Layer v6.1 Core, released in ISE design tools 11.3, and contains the following information:

- New Features

- Bug Fixes

- General Information

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:



New Features in v6.1

- ISE 11.3 software support

- Device support for all Virtex-6 FPGA subfamilies, including Virtex-6 LXT/SXT/CXT/HXT and Virtex-6 -1L devices

- Synopsys VCS simulator support

Bug Fixes in v6.1

- Failure in MAP with the following two error messages:

"ERROR:Pack:2310 - Too many comps of type "RAMB16BWE" found to fit this


"ERROR:Map:237 - The design is too large to fit the device."

- Version fixed: v6.1

- Description: Increased the size of the default part targeted in the Spartan-3AN FPGA example design. Fixes map errors in cores with a 32-bit data width and 4096-deep Block RAM FIFOs.

(Xilinx Answer 34527) Some designs may fail timing

- CR 510018

-Modified Spartan-3AN FPGA DCM phase shifts to achieve timing closure in 11.3

- Fixed issue in the GUI in which the TX and RX FIFO options had been disabled for all devices

- CR 510710

General Information

- The Tx and Rx cores are provided with default timing constraints in the UCF file generated with the core. Depending on the core configuration, target architecture, and speed grade, the core might run significantly faster. The user can modify the constraints to meet their performance requirements. As long as all timing constraints are met, the SPI-3 Link Core will operate at the user specified rate. Note that the best way to verify timing closure is with user logic, rather than the example design. Implementing only the example design might artificially limit the performance of the SPI-3 Link Core (e.g., if the User Interface is routed to I/O pins).

- A DCM with a PHASE_SHIFT on its clock is required to meet the OIF specification's 2 ns input timing requirement for Spartan-3/3E devices. This solution is necessary only if the system's timing budget cannot permit the Link Core to exceed the 2 ns input requirement.

Known Issues in v6.1

(Xilinx Answer 33589) MMCM multiply and divide values for Virtex-6 core incorrect

- CR 535086

Revision History

09/16/2009 - Initial Release

09/30/2009 - Added 33589 to Known Issues

AR# 33314
Date Created 09/09/2009
Last Updated 05/19/2012
Status Active
Type Known Issues