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Block Memory Generator v3.3 - Why do I see setup violations when I simulate my Virtex-6 device SDP memory?

AR# 33322

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Topic IP-SysLogic-BlockMem Generator
Last Updated 09/08/2009
Status Active
Description

Keywords: core, timing, block RAM, simple dual port

Why do I see setup violations between CLKARDCLK and REGCEAREGCE when I simulate my Virtex-6 device Simple Dual Port (SDP) block memory, and how do I solve this issue?

Solution

These setup violations can be safely ignored in this instance as they are on ports which are not actually used in the SDP Block Memory Generator v3.3 Core.

These setup violations will not affect the core functionality in any way and are scheduled to be fixed in ISE 11.4.
 
 
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