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AR# 33322

Block Memory Generator v3.3 - Why do I see setup violations when I simulate my Virtex-6 device SDP memory?


Why do I see setup violations between CLKARDCLK and REGCEAREGCE when I simulate my Virtex-6 device Simple Dual Port (SDP) block memory, and how do I solve this issue?


These setup violations can be safely ignored in this instance as they are on ports which are not actually used in the SDP Block Memory Generator v3.3 Core.  


These setup violations will not affect the core functionality in any way and are scheduled to be fixed in ISE 11.4.

AR# 33322
Date Created 09/07/2009
Last Updated 05/23/2014
Status Archive
Type General Article