Keywords: timing, TEMAC, MAC, hard TEMAC
When the Ethernet MAC is configured to use the 16-bit client interface, most transmit-side client signals are synchronous to PHYEMACMIITXCLK and most receive-side client signals are synchronous to PHYEMACRXCLK, as can be seen in the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide (UG368), figure 6-20.
http://www.xilinx.com/support/documentation/user_guides/ug368.pdfHowever, the ISE tools incorrectly analyze the transmit-side paths as if they were synchronous to CLIENTEMACTXCLIENTCLKIN and the receive-side paths as if they were synchronous to CLIENTEMACRXCLIENTCLKIN, as is the case for 8-bit client modes.
Since the clock net driving CLIENTEMACTX/RXCLIENTCLKIN runs at twice the frequency of client logic, this error results in over-constrained paths and might cause difficulty achieving timing closure.