We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33369

11.3 Spartan-3E device PlanAhead tool - Why am I allowed to put output pins at some Input Only Pins?


When I place a bidirectional or output pin in the PlanAhead tool, I am allowed to place it at some input only sites with no DRC errors. The implementation tools do report an error for these I/Os. Why is this the case and for what pins?


There is a problem in the PlanAhead tool where multi-purpose Input Only Pins do not have correct DRCs processed. For example, the pin named "IP_L16N_0" would be checked for Input Only, while the pin named "IP_L10P_0/GCLK8" would not.

To work around these errors, move your I/O to a valid site. PlanAhead software is not intended to be a sign-off tool, but is intended to catch as many violations as possible. Refer to (Xilinx Answer 32379).

AR# 33369
Date Created 09/01/2009
Last Updated 12/15/2012
Status Active
Type General Article