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AR# 33378

MIG v3.2, Virtex-6 FPGA QDRII+/RLDRAMII - Half-cycle path from ISERDES to clk_RD is not required

Description

The MIG 3.2 generated UCF for the Virtex-6 FPGA QDRII+ and RLDRAMII design contains a half-cycle path constraint from the ISERDES outputs to the falling edge of clk_rd. This constraint is not required.

Solution

Please remove the constraint similar to the following from your output UCF.

QDRII+ 

 #half cycle constraint for ISERDES outputs when clock inversion is used 

 NET "u_user_top/*/iserdes_*d*_int" TNM = TNM_iserdes_outputs; 

 TIMESPEC "TS_clk_rd_half_cycle" = FROM "TNM_iserdes_outputs" TO "FFS" TS_clk_rd/2;

RLDRAMII 

 #half cycle constraint for ISERDES outputs when clock inversion is used 

 NET "*iserdes_*d*_int" TNM = iserdes_outputs; 

 TIMESPEC "TS_clk_rd_half_cycle" = FROM "iserdes_outputs" TO "FFS" TS_clk_rd/2;

AR# 33378
Date Created 09/09/2009
Last Updated 05/23/2014
Status Archive
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG