11.2 EDK, MPMC v5.02.a - Single PLB memory writes corrupted in Spartan-6

AR#	33385	Search For Another Answer
Topic	EDK-IP-Memory-MPMC
Last Updated	09/04/2009
Status	Active

Description

Keywords: MCB

When performing a PLB write transaction of a single data beat to the MPMC over the PLB bus, the data is corrupted in memory.

How do I resolve this issue?

Solution

This issue is caused by a slow PLB clock frequency relative to a high external memory clock frequency. This results in a condition where the memory controller requests data before the PLB data phase can be fully completed to the memory FIFO. This failure has been observed with a 66 MHz PLB and 800 MHz memory clock.

To work around this issue, changing the PLB clock to 66 MHz or the memory clock to 600 MHz will avoid the issue.

This is planned to be fixed in MPMC v5.04.a, to be released in EDK 11.4.