I am running the Partial Reconfiguration flow on a design which contains a MIG or PCIe core. During mapping of configurations which import these cores, it fails in phase x.37 with no meaningful error message. How do I get past this issue?
There is a patch available for this specific issue in the Partial Reconfiguration Flow. If you believe you have run into this issue, please contact Xilinx Technical Support to obtain the patch.