Keywords: core, generator, FIFO18, FIFO18E1
When I generate a Common Clock FIFO for my Virtex-6 device and target the Built In FIFO, the DOUT reset value does not function correctly. Why?
This is a known issue in v5.3 of the FIFO Generator and affects Virtex-6/-6L devices which target a Common Clock, Built In FIFO, with a data width of >18 and <= 36, and which uses the embedded output register.
This issue is scheduled to be fixed in the 12.1 ISE release.