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AR# 33395

FIFO Generator v5.3 - DOUT reset value does not function correctly on a Virtex-6 device Built In FIFO


Keywords: core, generator, FIFO18, FIFO18E1

When I generate a Common Clock FIFO for my Virtex-6 device and target the Built In FIFO, the DOUT reset value does not function correctly. Why?


This is a known issue in v5.3 of the FIFO Generator and affects Virtex-6/-6L devices which target a Common Clock, Built In FIFO, with a data width of >18 and <= 36, and which uses the embedded output register.

This issue is scheduled to be fixed in the 12.1 ISE release.
AR# 33395
Date 09/08/2009
Status Active
Type General Article
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