UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33400

Endpoint Block Plus Wrapper v1.12 for PCI Express - ModelSim simulation results in numerous signals trimmed from the wave dump

Description


Known Issue: v1.11, v1.10.1, v1.10, v1.9.4, v1.9.3, v1.9.2, v1.9.1, v1.9, v1.8, v1.7.1, v1.6.1, v1.5, v1.4, v1.2, v1.1 
 
Simulations with newer versions of ModelSim might not contain all signals in the design.

Solution


ModelSim trims some signals out of the design. To avoid this, add -voptargs="+acc" to simulate_mti.do. 
 
vsim +notimingchecks -t 1ps +TESTNAME=sample_smoke_test0 -voptargs="+acc" -L work -L secureip -L unisims_ver work.board glbl 
 
Revision History 
09/16/2009 - Initial Release
AR# 33400
Date Created 09/08/2009
Last Updated 08/26/2013
Status Active
Type General Article
IP
  • Endpoint Block Plus Wrapper for PCI Express