MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - Simulation warnings are generated for mismatches in port connection sizes

AR#	33403	Search For Another Answer
Topic	MIG
Last Updated	06/13/2011
Status	Active

Description

When simulating the MIG v3.2 Virtex-6 DDR3 and DDR2 SDRAM UDIMM designs, the following warnings are generated:


 # ** Warning: (vsim-3015) sim_tb_top.v(608): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'cs_n'. 

 # ** Warning: (vsim-3015) sim_tb_top.v(608): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'odt'

Solution

These warnings occur because of signal port width mismatches in the sim_tb_top.v testbench module. For UDIMM designs, the CS and ODT signal widths are 2. However, in the testbench (sim_tb_top.v) only 1 bit is port mapped to the memory model instance.

To work around these warnings, replace the following code in the sim_tb_top.v module: 

Original Code 

.cs_n (ddr2_cs_n_sdram), 

.odt (ddr2_odt_sdram)

Workaround  

.cs_n (ddr2_cs_n_sdram[i/8]), 

.odt (ddr2_odt_sdram[i/8])

These changes to the sim_tb_top.v module are included in MIG v3.3 and available with ISE Design Suite 11.4.