11.3 EDK, plbv46_pcie_v4_01_a - Bridge does not complete the PLB to PCIe write request and hangs

Description

In the test_hello_world, the Virtex-6 FPGA End Point bridge receives a PCIe to PLB write request at the same time as a PLB to PCIe write request. The PLB to PCIe write request is never completed on the PLB and hangs the bus. The PCIe to PLB write request never goes through the bridge. Previous to this, there is a PCIe to PLB read request that completes correctly.

Solution