We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33408

11.3 EDK, plbv46_pcie_v4_01_a - Bridge does not complete the PLB to PCIe write request and hangs


In the test_hello_world, the Virtex-6 FPGA End Point bridge receives a PCIe to PLB write request at the same time as a PLB to PCIe write request. The PLB to PCIe write request is never completed on the PLB and hangs the bus. The PCIe to PLB write request never goes through the bridge. Previous to this, there is a PCIe to PLB read request that completes correctly.


This has been fixed in the latest PLBv46_pcie core, and is available in EDK 11.3. 

EDK 11.3 is available at:  

AR# 33408
Date 05/23/2014
Status Archive
Type General Article
  • EDK - 11.3
Page Bookmarked