Starting with MIG v3.2, Virtex-6 FPGA DDR2 and DDR3 designs support data widths greater then 72-bits (please see the Virtex-6 FPGA Memory Interface Solutions User Guide (ug406) for full details on data width support). The Traffic Generator, however, does not include logic to support widths above 72-bits.
The Traffic Generator also does not include logic to support Burst Length of 4 DDR2 designs.
Because the Traffic Generator is not designed to support data widths greater than 72-bits or DDR2 BL4, it does not simulate or implement in hardware properly (for these cases only). There are no issues with the actual MIG DDR2/DDR3 designs, only with the Traffic Generator, which is included in the example design.
Logic to support both data widths greater then 72-bits and DDR2 BL4 will be added in MIG v3.3 which will be available with IDS 11.4.