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AR# 33409

MIG v3.2, Virtex-6 FPGA DDR2 and DDR3 - Traffic Generator (example_design) does not support DDR2 BL=4 and DDR2/DDR3 Data Widths greater then 72-bits


Starting with MIG v3.2, Virtex-6 FPGA DDR2 and DDR3 designs support data widths greater then 72-bits (please see the Virtex-6 FPGA Memory Interface Solutions User Guide (ug406) for full details on data width support).

However the Traffic Generator does not include logic to support widths above 72-bits.

The Traffic Generator also does not include logic to support DDR2 designs with a Burst Length of 4.


Because the Traffic Generator is not designed to support data widths greater than 72-bits or DDR2 BL4, it does not simulate or implement in hardware properly (for these cases only).

There are no issues with the actual MIG DDR2/DDR3 designs, only with the Traffic Generator, which is included in the example design.

Logic to support both data widths greater then 72-bits and DDR2 BL4 will be added in MIG v3.3 which will be available with IDS 11.4.
AR# 33409
Date Created 09/09/2009
Last Updated 08/14/2014
Status Active
Type General Article
  • Virtex-6 CXT
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