UCF Modifications for Single Controller Designs
Add the following constraint to the 'example_design/par/example_top.ucf' and/or the 'user_design/par/mig_32.ucf' file:
# constraint SYSTEM IN clock
NET "u_clk_ibuf/sys_clk_ibufg" TNM_NET = TNM_sys_clk_ibufg;
TIMESPEC "TS_sys_clk_ibufg" = PERIOD "TNM_sys_clk_ibufg" <clock period> ns HIGH 50 %;
UCF Modifications for Multiple Controller Designs
Add the following constraint to the 'example_design/par/example_top.ucf' and/or the 'user_design/par/mig_32.ucf' file:
# constraint SYSTEM IN clock
NET "u_clk<frequency>_ibuf/sys_clk_ibufg" TNM_NET = TNM_sys_clk<frequency>_ibufg;
TIMESPEC "TS_sys_clk<frequency>_ibufg" = PERIOD "TNM_sys_clk<frequency>_ibufg" <clock period> ns HIGH 50 %;
Where:
<clock_period> -> clock period value
Ex: For 350 MHz frequency, the <clock_period>value is 2.857
<frequency> -> frequency value in MHz (only integer value)
Ex: For 350 MHz frequency, the <frequency> value is 350
For multiple controller designs, the controllers that have the same design frequency will have the clocking constraints declared only once in the UCF file. For example, for a three controller design with frequencies of 350 MHz, 400 MHz and 400 MHz, the UCF will have only two system clock constraints declared:
#constraint SYSTEM IN clock
NET "u_clk350_ibuf/sys_clk_ibufg" TNM_NET = TNM_sys_clk350_ibufg;
TIMESPEC "TS_sys_clk350_ibufg" = PERIOD "TNM_sys_clk350_ibufg" 2.857 ns HIGH 50 %;
#constraint SYSTEM IN clock
NET "u_clk400_ibuf/sys_clk_ibufg" TNM_NET = TNM_sys_clk400_ibufg;
TIMESPEC "TS_sys_clk400_ibufg" = PERIOD "TNM_sys_clk400_ibufg" 2.5 ns HIGH 50 %;
BUFR Constraint Modifications to UCF File
Modify the following constraint in the 'example_design/par/example_top.ucf' and/or the 'user_design/par/mig_32.ucf' file such that the period is half of the design frequency. For multi controller designs, this constraint will be included multiple times (once for each controllers).
#constraint QDR_CQ_P/N clocks
NET "u_user_top/*/clk_rd" TNM_NET = TNM_clk_rd;
TIMESPEC "TS_clk_rd" = PERIOD "TNM_clk_rd" <half_clk_period> ns HIGH 50 %;