MIG v3.2, Virtex-6 FPGA DDR2DDR3 - Master Bank selection is not enabled in some cases which require a Master Bank

AR#	33415	Search For Another Answer
Topic	MIG
Last Updated	06/09/2011
Status	Active

Description

MIG v3.2 does not enable the Master Bank selection box for specific Virtex-6 FPGA DDR2/DDR3 designs even though a Master Bank is required.  

The tools allow the design to generate, but the following error occurs during MAP: 

ERROR:Place:899 - The following IOBs use the DIgitally Controlled Impedance feature (DCI) and have been locked (LOC constraint) to the I/O bank 33. This feature requires the VRN and VRP pins within the same I/O bank to be connected to reference resistors. The following VR pins are currently locked and cannot be used to supply the necessary reference. 

IO Standard: Name = DIFF_SSTL15_T_DCI, VREF = NR, VCCO = 1.50, TERM = SPLIT, DIR = BIDIR, DRIVE_STR = NR 

List of locked IOB's: 

ddr3_ck_n<0> 
ddr3_ck_p<0> 

List of occupied VR Sites: 

VR site IOB_X2Y55 is occupied by comp phy_init_done 

The specific cases where this is seen are when VRN/VRP pins are utilized in a bank by Address/Control or System Control groups.

Solution

To work around this issue, users must manually add the DCI Cascade syntax in the generated UCF file. 

CONFIG DCI_CASCADE = "<master> <slave1> <slave2>..."; 

The master bank must be assigned to a bank in the same column of the bank in which the VRN/VRP pins are utilized. The banks in which the VRN/VRP pins are utilized for general pin allocation should be added as Slave banks. The master bank should have VRN/VRP pins available, and at least one input/inout pin with the same I/O Standard as that of Slave bank. If not, then assign a input/inout pin in the Master bank with the same I/O Standard as that of Slave bank, and add the dummy logic related to the Master bank input/input pin in the design top rtl file. 

If you need assistance in creating this constraint/dummy logic, please open a webcase and include the datasheet.txt for the generated MIG core: http://www.xilinx.com/support/clearexpress/websupport.htm

To see a working example, generate a MIG design with Master Bank enabled.  

This issue will be resolved in MIG v3.3 - released with ISE Design Suite 11.4.