To work around this issue, users must manually add the DCI Cascade syntax in the generated UCF file.
CONFIG DCI_CASCADE = "<master> <slave1> <slave2>...";
The master bank must be assigned to a bank in the same column of the bank in which the VRN/VRP pins are utilized. The banks in which the VRN/VRP pins are utilized for general pin allocation should be added as Slave banks. The master bank should have VRN/VRP pins available, and at least one input/inout pin with the same I/O Standard as that of Slave bank. If not, then assign a input/inout pin in the Master bank with the same I/O Standard as that of Slave bank, and add the dummy logic related to the Master bank input/input pin in the design top rtl file.
If you need assistance in creating this constraint/dummy logic, please open a webcase and include the datasheet.txt for the generated MIG core:
http://www.xilinx.com/support/clearexpress/websupport.htm To see a working example, generate a MIG design with Master Bank enabled.
This issue will be resolved in MIG v3.3 - released with ISE Design Suite 11.4.