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AR# 33418 MIG v3.2, v3.3, Virtex-6 FPGA DDR3 - When I target a RDIMM with CWL=7, the design does not drive the correct write data in OTF mode

Description

The MIG v3.2/v3.3 Virtex-6 FPGA DDR2 design that targets a RDIMM with CWL=7 violates a DFI timing specification. The DFI interface between the Memory controller and PHY layer is violating the tCNFG2WR__EN timing. As per the DFI specifications, the tCNFG2WR_EN value should be evaluated by the equation tCNFG2WR_EN = 2 + floor(0.5*(CWL-5)). For CWL equal to 7, this value should be 3, but the controller is driving a value of 2. Due to this incorrect value for the tCNFG2WR_EN parameter, write data for particular write transactions are not correct.

Solution

This issue occurs on write data when running in OTF (on-the-fly) burst mode. For example, data might be driven correctly for a first write with a BC4 operation, but then incorrectly for a next write with a BL8 operation.

This issue is resolved in MIG v3.4 (available with ISE Design Suite 12.1).

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AR# 33418
Date Created 09/09/2009
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
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IP
  • MIG
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