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AR# 33433 ISE Simulator (ISim) - "FATAL_ERROR:Simulator:CompilerAssert.h:40:1.36.10.7..."

Description


The following error occurs when I run a simulation on a design:

"FATAL_ERROR:Simulator:CompilerAssert.h:40:1.36.10.7 - Internal Compiler Error in file ../src/VhdlDecl.cpp at line 3187 Process will terminate.

For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support."

How can I resolve this issue?

Solution

  • An issue in ISE Update 2 (11.2) and older versions caused certain designs with IP cores to cause this error.
    This issue has been fixed in ISE Design Suite 11 Update 3 (11.3). Please download and install the latest ISE Design Suite update from the Download Center at: http://www.xilinx.com/support/download/index.htm
  • Designs with conditional delays, such as the following, asserted this fatal error:
    assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;

    This issue has been fixed by ISE Design Suite 11 Update 2 (11.2). Please download and install the latest ISE Design Suite update from the Download Center at: http://www.xilinx.com/support/download/index.htm
  • An issue in 12.1 and older caused designs that had custom vhdl data types to issue this Fatal Error.
     The issue is as follows with a function definitions.

    function "+"(X,Y:work.COMPLEX.REAL_VECTOR) return work.COMPLEX.REAL_VECTOR is

    If the definition is changed to the following and use work.COMPLEX.all this will resovle the fatal error.

    function "+"(X,Y:REAL_VECTOR) return work.COMPLEX.REAL_VECTOR is

    This issue has been fixed by ISE Design Suite 12.2. Please download and install the latest ISE Design Suite update from the Download Center at: http://www.xilinx.com/support/download/index.htm

Actions

AR# 33433
Date Created 09/08/2009
Last Updated 11/03/2010
Status Active
Type
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