AR# 33439 MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - ECC not supported for data widths equal to 120-bit

Description
Solution

The MIG v3.2 Virtex-6 FPGA DDR2/DDR3 design has an issue with the H-Matrix generated by the ECC code for data widths equal to 120-bits. Therefore, this configuration cannot support ECC with the MIG v3.2 release.

This issue is resolved in MIG v3.3, available with ISE Design Suite 11.4.

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AR# 33439
Date Created	09/09/2009
Last Updated	06/13/2011
Status	Active
Type
Devices	Virtex-6 CXT Virtex-6 HXT Virtex-6 LX More Virtex-6 LXT Virtex-6 SXT Less
IP	MIG

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AR# 33439 MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - ECC not supported for data widths equal to 120-bit

Description

Solution

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