UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33441

MIG v3.2, v3.3, Virtex-6 FPGA DDR2/DDR3 - Periodic reads associated with the phase detector are not properly sent according to the tPRDI timing parameter

Description

The MIG v3.2/v3.2 DDR2/DDR3 design issues periodic reads as a part of the phase detector circuit to maintain the data capture window over VT variations.

The tPRDI parameter defines the time period between the periodic reads.

During idle bus time, the time period defined by this parameter ensures that a read is sent to monitor DQS and performs any adjustment needed.

Please see the Virtex-6 FPGA Memory Interface Solutions User Guide (UG406) for full details.

In some cases, this read is not sent according to the tPRDI parameter.

Solution

This issue occurs in cases where the tREFI period is greater than the tPRDI period. 

This has minimal effect as the periodic read is sent approximately 30 clock cycles later, allowing the phase detection to complete. 

This issue is resolved in MIG v3.4, which was released with ISE Design Suite 12.1.

AR# 33441
Date Created 09/09/2009
Last Updated 08/18/2014
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG