The MIG v3.2 Virtex-6 FPGA DDR3 design might encounter tRP violations in simulation. This is because of a rounding error in the design.
The allowed values for Write Recovery for DDR3 are 5, 6, 7, 8, 10, 12 and these values are calculated by rounding off the value of 15000/tCK to the next integer. In cases where 15000/tCK is evaluated between 8 and 9, the Write Recovery should be rounded off to 10. The controller however, is rounding off to 9 for conditions where 15000/tCK is greater than 8, but less than 9. This is resulting in tRP (Read/Write to precharge) violations at the Memory Side. These violations can be ignored.
The rounding issue is fixed in MIG v3.3, which is available with ISE Design Suite 11.4.
- Virtex-6 CXT
- Virtex-6 HXT
- Virtex-6 LX
- Virtex-6 LXT
- Virtex-6 SXT