Serial RapidIO v5.4 - VHDL example design simulation error when CRF bit de-selected
Description
Keywords: phy_wrapper, MMCM, SRIO, rapid, IO
When simulating a RapidIO v5.4 core with VHDL source, the simulation produces the following error:
"../../example_design/phy_wrapper.vhd(365): Illegal target for signal assignment."
This error happens only when the user de-selects the CRF bit in the core's customization GUI, page 2.
Solution
To work around this issue, remove the following 2 lines from the phy_wrapper.vhd file:signal lnk_rcrf_int : std_logic;
lnk_rcrf <= lnk_rcrf_int;
This issue will be fixed in the next Serial RapidIO core release.
Revision History
09/16/2009 - Initial Release