Serial RapidIO v5.4 - VHDL example design simulation error with core_clk.vhd

AR#	33453	Search For Another Answer
Topic	IP-RapidIO-Serial
Last Updated	09/11/2009
Status	Active

Description

Keywords: core_clk, MMCM, SRIO, rapid, IO

When simulating a Virtex-6 FPGA RapidIO v5.4 core, with x1 lane width and 1.25G line rate, the VHDL simulation produces the following error:

"../../example_design/core_clk.vhd(131): Integer literal 13 is not of type std.standard.real."

Solution

To work around this issue, change the CLKOUT0_DIVIDE_F attribute value of the MMCM from "13" to "13.0"

This issue will be fixed in the next core release.

Revision History
09/16/2009 - Initial Release