1) The wrong Clock Correction sequence is being used for Virtex-6 FPGA. This causes the link to continuously go down then back up with the port_initialized signal de-asserting. The following attribute must be changed in the GTX wrapper file ("gtx_wrapper_gtx.v") as follows:
.CLK_COR_SEQ_1_1 (10'b0111111101),
This issue is scheduled to be fixed in the RocketIO Virtex-6 GTX Wizard and RapidIO v5.5 core in ISE Design Suite 12.1. CR 535430
2) Virtex-6 GTX FPGA clock correction must be changed to a 2-byte sequence, with each byte set for the /R/ character (K29.7). The method for changing this is similar to that described in (Xilinx Answer 32188).
This issue is scheduled to be fixed in the RocketIO Virtex-6 GTX Wizard and RapidIO v5.5 core in ISE Design Suite 12.1. CR 535314, CR 535221.
3) When using the x4 lane, 3.125 Gb/s, 125mhz core only, the clock parameters are incorrect. This causes the link to come up only ~50% of the time. To work around the issue, change the following lines in "<core_name>_clk.v(vhd)" as follows:
.CLKFBOUT_MULT_F (5.000),
.CLKOUT0_DIVIDE_F (5.000),
.CLKOUT1_DIVIDE (20),
.CLKIN1_PERIOD (8.0),
4) For 3.125 Gb/s, 156 MHz Virtex-6 FPGA cores the TX and RX PLL parameters are incorrect in the GTX wrapper files. CR 535503
This can be fixed by generating a new wrapper from the RocketIO wizards using the provided XCO files, located at:
http://www.xilinx.com/txpatches/pub/swhelp/coregen/33454_srio_xco_files.zip
There are two options available:
For x4:
Change fifo_upper_bounds=22 to fifo_upper_bounds=24
For x1:
Change fifo_upper_bounds=16 to fifo_upper_bounds=18
5) The x4 lane cores have an issue with channel bonding where the RX buffer pointers were not being reset often enough, preventing the lanes from channel bonding. This is apparent when comparing the individual RXDATA buses from each MGT, which shows that the MGT data is not aligned. Also, in x4 mode the core will train to x1 lane 60% of the time. CR 535500
To fix this, the following modifications are needed in the "srio_gt_wrapper_v6_4x.v" file.
The txreset1 and txreset3 signals must be reset on "fall_txinhibit02_q" instead of "fall_txinhibit13_q":
Change FROM:
always @(posedge RXUSRCLK2 or posedge GTPRESET) begin
if (GTPRESET)
RXBUFERR <= #Tcq 1'b0;
else begin
if (CHBONDDONE0 && CHBONDDONE1 && CHBONDDONE2 && CHBONDDONE3)
RXBUFERR <= #Tcq rxbuferr0 || rxbuferr1 || rxbuferr2 || rxbuferr3;
else if (rxelecidle0) //removed
RXBUFERR <= #Tcq rxbuferr2;
else
RXBUFERR <= #Tcq rxbuferr0;
end
end
Change TO:
always @(posedge RXUSRCLK2 or posedge GTXRESET) begin
if (GTXRESET)
RXBUFERR <= #Tcq 1'b0;
else begin
if (fall_txinhibit02_q || fall_txinhibit13_q) //added
RXBUFERR <= 1'b1;
else if (CHBONDDONE0 && CHBONDDONE1 && CHBONDDONE2 && CHBONDDONE3)
RXBUFERR <= #Tcq rxbuferr0 || rxbuferr1 || rxbuferr2 || rxbuferr3;
else
RXBUFERR <= #Tcq rxbuferr0;
end
end
- The RXBUFERR signal must assert when either "fall_txinhibit02_q" or "fall_txinhibit13_q" asserts:
Change FROM:
always @(posedge TXUSRCLK2 or posedge GTXRESET) begin
if (GTXRESET)
txreset0 <= #Tcq 1'b0;
else
txreset0 <= #Tcq txresetdone0 & (TXBUFSTATUS0[1] || fall_txinhibit02_q);
end
always @(posedge TXUSRCLK2 or posedge GTXRESET) begin
if (GTXRESET)
txreset1 <= #Tcq 1'b0;
else
txreset1 <= #Tcq txresetdone1 & (TXBUFSTATUS1[1] || fall_txinhibit13_q);
end
always @(posedge TXUSRCLK2 or posedge GTXRESET) begin
if (GTXRESET)
txreset2 <= #Tcq 1'b0;
else
txreset2 <= #Tcq txresetdone2 & (TXBUFSTATUS2[1] || fall_txinhibit02_q);
end
always @(posedge TXUSRCLK2 or posedge GTXRESET) begin
if (GTXRESET)
txreset3 <= #Tcq 1'b0;
else
txreset3 <= #Tcq txresetdone3 & (TXBUFSTATUS3[1] || fall_txinhibit13_q);
end
Change TO:
always @(posedge TXUSRCLK2 or posedge GTXRESET) begin
if (GTXRESET)
txreset0 <= #Tcq 1'b0;
else
txreset0 <= #Tcq txresetdone0 & (TXBUFSTATUS0[1] || fall_txinhibit02_q);
end
always @(posedge TXUSRCLK2 or posedge GTXRESET) begin
if (GTXRESET)
txreset1 <= #Tcq 1'b0;
else
txreset1 <= #Tcq txresetdone1 & (TXBUFSTATUS1[1] || fall_txinhibit02_q);
end
always @(posedge TXUSRCLK2 or posedge GTXRESET) begin
if (GTXRESET)
txreset2 <= #Tcq 1'b0;
else
txreset2 <= #Tcq txresetdone2 & (TXBUFSTATUS2[1] || fall_txinhibit02_q);
end
always @(posedge TXUSRCLK2 or posedge GTXRESET) begin
if (GTXRESET)
txreset3 <= #Tcq 1'b0;
else
txreset3 <= #Tcq txresetdone3 & (TXBUFSTATUS3[1] || fall_txinhibit02_q);
end
- All rxelecidle signals should be removed from the wrapper as these were not being generated properly and are not being used.
Revision History
09/16/2009 - Initial Release
10/27/2009 - Added Issues 1 through 5