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AR# 33464

LogiCORE IP v1.3 CIC Compiler - Why do I get an error message during simulation that my RATE signal is out of range when my RATE_WE signal is not asserted?

Description

Why do I receive an error message during simulation that my RATE signal is out of range when my RATE_WE signal is not asserted?

Solution

The behavioral model can issue an invalid error due to a check on the RATE port that it is within the valid range as specified in the GUI. 

 

Currently, this DRC issues an error if the RATE input exceeds the valid range for the RATE input while RATE_WE is undefined.  

 

This issue will be addressed in a future release.

AR# 33464
Date Created 09/09/2009
Last Updated 05/23/2014
Status Archive
Type General Article