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AR# 33470

Virtex 6 GTH Transceiver Wizard - v1.1 Release Notes and Known Issues

Description

This Answer Record contains the revision notes and an updated known issues list for the Virtex-6 GTH Transceiver Wizard v1.1.

Solution

INTRODUCTION 

For the most recent updates to the IP installation instructions for this core, 

please go to: 

 

http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
 

For system requirements: 

 

http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
 

This file contains release notes for the Xilinx Virtex-6 FPGA GTH Transceiver Wizard v1.1. For the latest core updates, see the product page at: 

 

http://www.xilinx.com/content/xilinx/en/products/intellectual-property/v6_fpga_gth_transceiver_wizard.html

 

NEW FEATURES 

 

- Xilinx ISE(R) 11.3 software support 

- Use one of the three available protocol templates 

 

KNOWN ISSUES 

The following are known issues for v1.1 of this core at time of release: 

 

- For HXT devices that have only one GTH column, upon recustomization of the core, both columns will appear in the GUI. To generate a proper wrapper when recustomizing for these devices, only select GTHE1_QUADS from the X1 (right) column. This issue does not present itself for HXT devices that have two GTH columns. 

 

- Virtex-6 solutions are pending hardware validation. The most recent information, including known issues, workarounds, and 

resolutions for this version is provided in the release notes Answer Record for the ISE 11.2 IP Update at: 

 

http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
 

TECHNICAL SUPPORT 

To obtain technical support, create a WebCase at: 

 

www.xilinx.com/support 

 

Questions are routed to a team with expertise using this product. Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines. 

 

CORE RELEASE HISTORY 

 

Date By Version Description 

================================================================================ 

09/16/2009 Xilinx, Inc. 1.1 Initial release 

================================================================================

AR# 33470
Date Created 09/14/2009
Last Updated 11/10/2014
Status Active
Type General Article