UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33474

11.3 XST/Synplify - What are the limitations for inferring block RAM in Spartan-6 FPGA architecture?

Description

Keywords: XST, Synplify, limitations, Block RAM, BRAM, Spartan-6, FPGA, 11.2, 11.3, 11.4

What are the limitations for inferring block RAM in Spartan-6 FPGA architecture?

Solution

Most inferred block RAM implementations are optimal for the Spartan-6 FPGA architecture. This solution record attempts to explain the current known limitations in trying to infer block RAMs using either Synplify 2009.06 or XST 11.3 software.

512 x 36 Single-Port RAM

For both XST and Synplify software, a single-port block RAM with a data width greater than 18 bits but less than or equal to 36 bits, and a depth of 256 bits or less, is implemented in a RAMB16 where it can be implemented in a RAMB8. Until this is corrected, it is suggested to either use CORE Generator or instantiate and connect the RAMB8 component to get the best utilization and power characteristics from the block RAM.

Simple Dual-Port Block RAM

XST and Synplify do not properly infer the RAMB8 for simple dual-port block RAMs with a data depth of 256 bits. The documentation for the latest version of the tool should be consulted to determine if this limitation still exists. Until this is corrected, it is suggested to either use CORE Generator or instantiate and connect the RAMB8 component to get the best utilization and power characteristics from the block RAM.

Block RAMs With Different Port Data-Width Values

XST and Synplify software cannot infer block RAMs with different data-widths on ports A and B. Such block RAMs must be instantiated to be incorporated into the design.


Block RAM Depth Not a Power of Two

If the block RAM depth is not defined as or desired to be a power of 2 (e.g., 512, 1024, 2048, etc.), CORE Generator software can sometimes implement a more area-efficient block RAM implementation in many cases.

AR# 33474
Date Created 09/10/2009
Last Updated 09/12/2009
Status Active
Type General Article