Wizard:

(Xilinx Answer 45686)Virtex-6 FPGA GTX Transceiver Wizard v1.12 -Known Issues and Release Notes
(Xilinx Answer 44489)Virtex-6 FPGA GTX Transceiver Wizard v1.11 -Known Issues and Release Notes
(Xilinx Answer 42806)Virtex-6 FPGA GTX Transceiver Wizard v1.10 -Known Issues and Release Notes
(Xilinx Answer 40739)Virtex-6 FPGA GTX Transceiver Wizard v1.9 -Known Issues and Release Notes
(Xilinx Answer 39757)Virtex-6 FPGA GTX Transceiver Wizard v1.8 - Release Notes and Known Issues for ISE Software 12.4
(Xilinx Answer 38396)Virtex-6 FPGA GTX Transceiver Wizard v1.7 - Release Notes and Known Issues for ISE Software 12.3
(Xilinx Answer 41612)Virtex-6 FPGA GTX Transceiver Wizard v1.6 - Release Notes and Known Issues for ISE Software 12.2
(Xilinx Answer 35265)Virtex-6 FPGA GTX Transceiver Wizard v1.5 - Release Notes and Known Issues for ISE Software 12.1
(Xilinx Answer 33864)Virtex-6 FPGA GTX Transceiver Wizard v1.4 - Release Notes and Known Issues for ISE Software 11.4
(Xilinx Answer 33469) Virtex 6 FPGA GTX Transceiver Wizard - v1.3 Release Notes and Known Issues
(Xilinx Answer 32746) Virtex 6 FPGA GTX Transceiver Wizard - v1.2 Release Notes and Known Issues
(Xilinx Answer 42592)Virtex-6 GTX Wizard - Support for Virtex-6Q Lower Power Devices in ISE 13.2 Software Release
(Xilinx Answer 32996) Virtex-6 FPGA GTX Transceiver Wizard - Timing not met on implemented example design
(Xilinx Answer 33625) Virtex-6 FPGA GTX Transceiver Wizard v1.3 - GUI does not support the maximum of 36 to 48 transceivers available on some devices
(Xilinx Answer 34143)Virtex-6 FPGA GTX Transceiver Wizard - Example MMCM causes errors
(Xilinx Answer 34192)Virtex-6 FPGA GTX Transceiver Wizard - Oversampling rate update for production silicon
(Xilinx Answer 34216)Virtex-6 FPGA GTX Transceiver Wizard - Unable to generate wrapper for line rates above 6.5 Gb/s
(Xilinx Answer 34138)Virtex-6 FPGA GTX Transceiver Wizard - Phase alignment not correct in hardware while using tx_sync module
(Xilinx Answer 34191)Virtex-6 FPGA GTX Transceiver Wizard - Attribute updates for production silicon
(Xilinx Answer 33994)Virtex-6 FPGA GTX Transceiver Wizard: Selecting "No TX" limits use of REFCLK0_Q0 for RX PLL
(Xilinx Answer 34992) Virtex-6 FPGA GTX Transceiver Wizard - Implementing updated -1 CXT GTX line rates
(Xilinx Answer 34539) Virtex-6 FPGA GTX Transceiver Wizard v1.4 - "Error: Integer literal 1 is not of type ieee.std_logic_1164.std_logic"

Usage:

(Xilinx Answer 39430) Virtex-6 GTX Transceiver - Delay Aligner Errata and Work-around
(Xilinx Answer 44208)Performance degradation of Xilinx Transceivers when using System Verilog with Synplify tool
(Xilinx Answer 32972) Virtex-6 FPGA - Far-End PCS Loopback data errors
(Xilinx Answer 33155) Virtex-6 FPGA GTX Transceiver - SATA Beaconing may transmit 2 or 4 extra characters upon exit of electrical idle
(Xilinx Answer 35386) Virtex-6/Spartan-6 FPGA - Does Spartan-6 or Virtex-6 have CRC hard blocks?
(Xilinx Answer 38241) Virtex-6 GTX Transceiver: Latency tables based on blocks used
(Xilinx Answer 35425) Virtex-6 GTX - max SATArate and max USERCLK2 frequency
(Xilinx Answer 36625) Virtex-6FPGA GTX Transceiver - RXSLIDE functionality for manual data alignment
(Xilinx Answer 38452) Virtex-6 GTX Transceiver: DRP Addresses above 0x42h may not respond under power-down or reset conditions
(Xilinx Answer 38506) Virtex-6 FPGA GTX Transceiver - Reference clock phase noise masks
(Xilinx Answer 38564) Variation in analog power supply voltage while powering up or down transceivers

Implementation:

(Xilinx Answer 34224)Virtex-6 FPGA GTX Transceiver - XxYx locations of the GTX in the CXT Data Sheet are incorrect
(Xilinx Answer 36314) Virtex-6 GTX - UCF Xx_Yx locations missing for CXT family
(Xilinx Answer 34028)Virtex-6 FPGAGTX Transceiver - Instantiating a dummy transceiver to allow for correct calibration
(Xilinx Answer 37014)Virtex-6 GTX Transceiver: ERROR:MapLib:1226 - GTXE1 - DRC Error when POWER_SAVE is set incorrectly
(Xilinx Answer 34452) Virtex-6 CXT: GTX pin/banking comparisons for FF(G)1156 package

ES Specific:

(Xilinx Answer 33227) Virtex-6 FPGA GTX Transceiver - Special considerations for RX Buffer Bypass in CES9980
(Xilinx Answer 38366) Virtex-6 GTX ES Devices - Glitches in TXOUTCLK

Simulation:

(Xilinx Answer 34420) Virtex-6 GTX: sis kit known issues