Currently the example design testbench uses two different 156.25 MHz clocks with edges that are not in phase. This can result in timing simulation failing with a timeout when using the 64-bit Internal Interface Example Design targeting a Virtex-6 FPGA.
This is scheduled to be fixed in the next releases of the cores.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 33302 | LogiCORE IP XAUI v9.1 and v9.1 rev1 - Release Notes and Known Issues for ISE Design Suite 11.3 and 11.5 | N/A | N/A |
| 33311 | LogiCORE IP RXAUI v1.1 and v1.1 rev1 - Release Notes and Known Issues for ISE 11.3 and ISE 11.5 | N/A | N/A |