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AR# 33489

LogiCORE XAUI v9.1 and RXAUI v1.1 - Timing Simulation Timeouts seen in Virtex-6 FPGA 64-bit Internal Interface Example Design

Description

Currently the example design testbench uses two different 156.25 MHz clocks with edges that are not in phase. This can result in timing simulation failing with a timeout when using the 64-bit Internal Interface Example Design targeting a Virtex-6 FPGA.

Solution

This is scheduled to be fixed in the next releases of the cores.

Linked Answer Records

Associated Answer Records

AR# 33489
Date Created 09/11/2009
Last Updated 05/23/2014
Status Archive
Type General Article