When running timing simulation with the XAUI Spartan-6 FPGA example design, I can see timeout.
If Spartan-6 timing simulation is needed with this version of the core, please open a technical support case.
http://www.xilinx.com/support/
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 33302 | LogiCORE IP XAUI v9.1 and v9.1 rev1 - Release Notes and Known Issues for ISE Design Suite 11.3 and 11.5 | N/A | N/A |