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AR# 33491

LogiCORE XAUI v9.1 - Timeout seen in Spartan-6 FPGA Example Design Timing Simulation

Description

When running timing simulation with the XAUI Spartan-6 FPGA example design, I can see timeout.

Solution

If Spartan-6 timing simulation is needed with this version of the core, please open a technical support case. 

 

http://www.xilinx.com/support/

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33302 LogiCORE IP XAUI v9.1 and v9.1 rev1 - Release Notes and Known Issues for ISE Design Suite 11.3 and 11.5 N/A N/A
AR# 33491
Date Created 09/11/2009
Last Updated 05/23/2014
Status Archive
Type General Article