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11.1 EDK, MPMC v5.02.a - VFBC Read FIFO misses data beat when VFBC<Port_Num>_Rd_Empty = '1'

AR# 33543

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Topic EDK-IP-Memory-MPMC
Last Updated 09/22/2009
Status Active
Description

Keywords: empty, corrupt

A beat of data is missed during VFBC reads when the read fifo goes empty (VFBC<Port_Num>_Rd_Empty = '1'). When the read FIFO becomes not empty, a beat of data is skipped. How do I resolve this issue?

Solution

Currently no workarounds are known. Contact Xilinx Technical Support for updated information:
http://www.xilinx.com/support/clearexpress/websupport.htm

This issue is currently planned to be fixed in MPMC v5.04.a, to be released in EDK 11.4.
 
 
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