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AR# 33543

11.1 EDK, MPMC v5.02.a - VFBC Read FIFO misses data beat when VFBC_Rd_Empty = '1'


A beat of data is missed during VFBC reads when the read fifo goes empty (VFBC<Port_Num>_Rd_Empty = '1'). When the read FIFO becomes not empty, a beat of data is skipped. How do I resolve this issue?


Currently no workarounds are known. Contact Xilinx Technical Support for updated information:


This issue is currently planned to be fixed in MPMC v5.04.a, to be released in EDK 11.4.

AR# 33543
Date Created 09/21/2009
Last Updated 12/15/2012
Status Active
Type General Article