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AR# 33549

LogiCORE Endpoint PIPE v1.8 for PCI Express - Provided UCF and Avnet PCIe PIPE Starter Board might tie sys_reset_n to a 2.5 V SSTL bank instead of a 3.3V LVTTL bank

Description


Known Issue: v1.8, v1.7, v1.6, v1.5, v1.4, v1.3, v1.2, v1.1

The provided UCF and the UCF for the Avnet PIPE Starter Kit ties the sys_reset_n pin to a 2.5V SSTL bank. This might cause problems with some systems.

The issue was seen specifically in an IBM x3250 server. The IBM Server is unable to initialize the LSI MPT ROM of the RAID controller when the card with this endpoint core is installed in the PCIe slot.

Solution


This situation occurs because the sys_reset_n is tied to a 2.5V SSTL bank. Customers who copy the PIPE starter kit schematics should be aware of this issue. The work-around is to:

Connect PERST# to a 3.3V I/O bank with no termination, or use a level translator or current limiting resistor (Xilinx Answer 20492.htm) to connect PERST# to a 2.5V bank with no termination.

The Avnet PIPE Starter Kit schematic was updated to contain this information:

NOTE TO DESIGNERS USING THIS CIRCUIT AS A REFERENCE DESIGN

PCIe signal PERST# is a 3.3V LVTTL signal (see PCI Express Card Electromechanical Specification, DC Specifications for PERST#). This implementation incorrectly ties this signal to a 2.5V FPGA bank and uses SSTL termination. Options for a correct implementation:
  • Connect PERST# to a 3.3V I/O bank with no termination
  • Use a level translator or current limiting resistor, see (Xilinx Answer 20492), to connect PERST# to a 2.5V bank with no termination

If you find that your board does not work in your host system with a known good PCIe FPGA image, a work-around exists for this board:
  1. Disconnect RP24 pins 4 and 5; wire a 56-ohm resistor to RP24 pins 4 and 5.
  2. Disconnect RP49 pin 6.

Revision History
7/23/2010 - Updated for ISE 12.2 and v1.8
9/22/2009 - Initial Release.
AR# 33549
Date Created 09/22/2009
Last Updated 07/08/2010
Status Active
Type Known Issues