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AR# 33554

ChipScope Pro - "WARNING:PhysDesignRules:372 - Gated clock. Clock net icon_ is source by a combinatorial pin..."


When I implement a design that includes a ChipScope core, I see the following messages at BitGen:

WARNING:PhysDesignRules:372 - Gated clock. Clock net icon_<netname> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

Is this warning safe to ignore?


The BSCAN primitive used by the ChipScope tool requires 1 extra bit to be shifted in on JTAG.

This extra bit is clocked by a non-global clock route which causes the warning.

This is by design in the IP and is implemented to save on global clock routing.

The warning can be safely ignored.
AR# 33554
Date Created 09/23/2009
Last Updated 12/04/2014
Status Active
Type General Article
  • ChipScope ILA
  • ChipScope ICON