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11.1 Virtex-6 FPGA Editor - The first time I bring up a component in Logic Block Editor, the Attributes and Nets do not appear

AR# 33571

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Topic SW-FPGA Editor
Last Updated 09/25/2009
Status Active
Description

Keywords: slice, MGT, RAM, IO

I have a Virtex-6 design which I am looking at in FPGA Editor. The first time I open a component in Logic Block Editor, it appears unused. None of the connections nor attributes appear.

How do I get around this?

Solution

This will be resolved in a future version of software.

To work around this in current software, close the Logic Block Editor and reopen it. Everything will appear normally when reopened.


 
 
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