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  1. Xilinx - All Programmable
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  3. AR# 33571: 11.1 Virtex-6 FPGA Editor - The first time I bring up a component in Logic Block Editor, the Attributes and Nets do not appear

AR# 33571

11.1 Virtex-6 FPGA Editor - The first time I bring up a component in Logic Block Editor, the Attributes and Nets do not appear

Description

I have a Virtex-6 design which I am looking at in FPGA Editor. The first time I open a component in Logic Block Editor, it appears unused. None of the connections nor attributes appear. 

 

How do I get around this?

Solution

This will be resolved in a future version of software. 

 

To work around this in current software, close the Logic Block Editor and reopen it. Everything will appear normally when reopened.

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
38597 LogiCORE IP Motion Adaptive Noise Reduction (MANR) v1.1 - Why is the Motion Adaptive Noise Reduction so large when using the pCore interface? N/A N/A
AR# 33571
Date 05/23/2014
Status Archive
Type General Article