Serial RapidIO - Recommended modifications to Example Design reset scheme
Description
Known Issue: v5.1, v5.1 Rev1, v5.2, v5.3, v5.4
The "rio_reset" module provided with the core's Example Design is inconsistent with the User Guide recommendations, and does not handle in-band resets. The following issues need to be addressed if using a Serial RapidIO v5.4 Core or earlier. This issue is fixed in v5.5 and later; however, another issue exists as documented in (Xilinx Answer 36342)
1. The LOG_RST_N input to the Buffer layer must be at least 4 clock cycles (UG503 indicates 3 cycles, which is incorrect).
2. The rio_reset module will typically only assert sys_reset_n for two clock cycles, rather than the 4 cycles required.
3. The lnk_reset_n output of the PHY only asserts for one clock cycle for each series of 4 in-band reset control symbols (LR_RD symbols). Since this reset should be used for the PHY side of the buffer, this does not meet the buffer reset requirements.
4. The lnk_reset_n output of the PHY should only be used to reset the PHY-side of the Buffer. Currently, it is used for other resets as well.
Solution
The correct reset structure should be as shown in the following figure.
A set of replacement example design files is available for x1 lane Verilog cores here:
http://www.xilinx.com/txpatches/pub/swhelp/ise11_updates/33574_srio_reset_update.zip
To use these files, replace the existing files in you x1 lane design with the new ones provided.
For x4 lane designs, the updated rio_reset.v module can be used directly; however, the new reset connections from the rio_reset.v module to the Logical, Buffer, and PHY layers will need to be connected as shown in the image above.
NOTE: These files do not alter the "EP_SIM" side of the Example Design simulation. This will not affect functionality unless the user sends in-band resets to the EP_SIM (that is, "Host") side of the simulation.
Revision History
09/25/2009 - Initial Release