Description
The Spartan-6 FPGA GTP does not start during JTAG configuration. This issue is listed in the Spartan-6 FPGA errata for General ES devices. The following solutions can be used for JTAG configuration of the Spartan-6 FPGA when GTPs are used in the FPGA.
This issue is limited only to the ES devices. It is fixed in the Spartan-6 Production devices.
For more FPGA Device Specific Issues and other Configuration Related Articles, see (Xilinx Answer 34104).
Solution
Solution 1 Use the iMPACT tool to load the bit file via JTAG with a special environment variable setting. Set the following environment variable:
set XIL_CONFIG_USE_ISC_DISABLE=true
And use iMPACT tool 11.3 or later to configure the FPGA via JTAG.
Solution 2 Use the ChipScope tool to load the bit file via JTAG with a special environment variable setting. Set the following environment variable:
set XIL_CONFIG_USE_ISC_DISABLE=true
And use the ChipScope tool 11.3 or later to configure the FPGA via JTAG.
Solution 3 Use the System ACE CF tool to configure the FPGA and use the iMPACT tool with a special environment variable setting to generate the ACE configuration file. Set the following environment variable:
set XIL_CONFIG_USE_ISC_DISABLE=true
And use the iMPACT tool 11.3 or later to generate the ACE file for the System ACE CF solution.
Solution 4 Use the STARTUP_SPARTAN6 primitive with external reference clock within the FPGA design. Instantiate the STARTUP_SPARTAN6 primitive in the FPGA design. Connect a free-running clock from an FPGA pin to the CLK input port of the STARTUP_SPARTAN6 primitive. The clock must have a frequency between 50 MHz to 100 MHz. Select the bitstream generator option StartUpClk:UserClk.
NOTE: Solution 4 is only applicable for JTAG configuration. The bitstream generator option StartUpClk:UserClk is not supported for non-JTAG configuration methods when a GTP transceiver is used in the applicable devices listed. For non-JTAG configuration methods, select the default bitstream generator option StartUpClk:CCLK.