Q1. What other Ethernet IP cores are available?
A1. See http://www.xilinx.com/ethernet for a list of IP Ethernet Cores.
Q2. Why am I experiencing problems with data reception or transmission?
A2. To get started debugging possible RX/TX data issues or link up issues, see the debugging Appendix in the XAUI User's Guide (UG150):
Q3. What is the latency through the core?
A3. See the Core Latency Appendix in the XAUI User's Guide (UG150):
Q4. What verification and testing has been done with the core?
A4. The XAUI core has been verified using both simulation and hardware testing.
The core has been tested at the University of New Hampshire (UNH).
For more information, see the Verification and Interoperability Appendix in the XAUI User's Guide (UG150):
Q5. How do I connect the XAUI core to the 10GEMAC LogiCORE system?
A5. See the Special Design Considerations -> Interfacing to the Xilinx XAUI Core section in the 10-Gigabit Ethernet MAC User's Guide (UG148):
Q6. How does Synchronization, Alignment, and Link Up work? How are Idles encoded and faults handled?
A6. See the debugging Appendix in the XAUI User's Guide (UG150):
Q7. Where can I find a reference design for the XAUI core?
A7. In addition to the Example Design provided when the core is generated in the CORE Generator software (see the Getting Started Guide for more details):
There is also the "10-Gigabit Ethernet Hardware Demonstration Platform Application Note" (XAPP955):
Q8. How is data transferred from the XAUI to the User interface?
A8. The XAUI core is an extension of the XGMII interface and as such there is no data-stripping happening within the core.
There is some translation of control characters as it goes on to the physical interface (serdes) so as to maintain synchronization and alignment of lanes.
However there will be no change in the data when presented to the XGMII interface on the receiving end.
For more information on XAUI, please refer to the IEEE 802.3 spec, that can be downloaded fromhttp://standards.ieee.org/about/get/802/802.3.html